module ETH_EVB_V1_4(
    input           ext_osc_clk     ,   // 20M
    input           sw_rst_n        ,
    input           uart0_rx        ,
    output  wire    uart0_tx
);

wire            mcu_clk             ;
wire            fpga_clk            ;
wire            pll_locked          ;
wire            sys_rst_n           ;
wire            por_locked          ;


pll_v1 u_pll_v1(
    .clkin0     (   ext_osc_clk     ), // i
    .locked     (   pll_locked      ), // o
    .clkout0    (   fpga_clk        ), // o
    .clkout1    (   mcu_clk         )  // o
);

por_v1_1 u_por_v1_1(
    .O          (   por_locked      )
);

assign  sys_rst_n = sw_rst_n & pll_locked & por_locked;

soc_system_v1 u_soc_system_v1(
    .m3soc_clk_o                (   mcu_clk         ),
    .m3soc_clken                (   1'b1            ),
    .m3soc_rstn                 (   sys_rst_n       ),
    .u_m3soc_uart0_cts_n_i      (                   ),
    .u_m3soc_uart0_dcd_n_i      (                   ),
    .u_m3soc_uart0_dsr_n_i      (                   ),
    .u_m3soc_uart0_ri_n_i       (                   ),
    .u_m3soc_uart0_dtr_n_o      (                   ),
    .u_m3soc_uart0_out1_n_o     (                   ),
    .u_m3soc_uart0_out2_n_o     (                   ),
    .u_m3soc_uart0_rts_n_o      (                   ),
    .u_m3soc_uart0_sin_i        (   uart0_rx        ),
    .u_m3soc_uart0_sout_o       (   uart0_tx        ),
    .u_m3soc_uart0_sir_in_i     (                   ),
    .u_m3soc_uart0_sir_out_n_o  (                   ),
    .u_m3soc_uart0_baudout_n_o  (                   )
);


endmodule